september 2000 ? 2000 fairchild semiconductor corporation FDW2502P rev. d (w) FDW2502P dual p-channel 2.5v specified powertrench ? ? ? ? mosfet general description this p-channel 2.5v specified mosfet is a rugged gate version of fairchild's semiconductor?s advanced powertrench process. it has been optimized for power management applications with a wide range of gate drive voltage (2.5v ?12v). applications ? load switch ? motor drive ? dc/dc conversion ? power management features ? ?4.4 a, ?20 v. r ds(on) = 0.035 ? @ v gs = ?4.5 v r ds(on) = 0.057 ? @ v gs = ?2.5 v. ? extended v gss range (12v) for battery applications. ? high performance trench technology for extremely low r ds(on) . ? low profile tssop-8 package. d 1 s 1 s 1 g 1 d 2 s 2 s 2 g 2 tssop-8 pin 1 8 7 6 5 1 2 3 4 absolute maximum ratings t a =25 o c unless otherwise noted symbol parameter ratings units v dss drain-source voltage ?20 v v gss gate-source voltage 12 v i d drain current ? continuous (note 1a) ?4.4 a ? pulsed ?30 p d power dissipation for single operation (note 1a) 1.0 w (note 1b) 0.6 t j , t stg operating and storage junction temperature range -55 to +150 c thermal characteristics r ja thermal resistance, junction-to-ambient (note 1a) 125 c/w (note 1b) 208 package marking and ordering information device marking device reel size tape width quantity 2502p FDW2502P 13?? 12mm 3000 units FDW2502P
FDW2502P rev. d (w) electrical characteristics t a = 25c unless otherwise noted symbol parameter test conditions min typ max units off characteristics bv dss drain?source breakdown voltage v gs = 0 v, i d = ?250 a ?20 v ? bv dss === ? t j breakdown voltage temperature coefficient i d = ?250 a, referenced to 25 c ?17 mv/ c i dss zero gate voltage drain current v ds = ?16 v, v gs = 0 v ?1 a i gssf gate?body leakage, forward v gs = ?12 v, v ds = 0 v ?100 na i gssr gate?body leakage, reverse v gs = 12 v, v ds = 0 v 100 na on characteristics (note 2) v gs(th) gate threshold voltage v ds = v gs , i d = ?250 a ?0.6 ?1.0 ?1.5 v ? v gs(th) === ? t j gate threshold voltage temperature coefficient i d = ?250 a, referenced to 25 c 3.1 mv/ c r ds(on) static drain?source on?resistance v gs = ?4.5 v, i d = ?4.4 a v gs = ?4.5 v, i d = ?4.4 , t j =125 c v gs = ?2.5 v, i d = ?3.3 a 0.028 0.039 0.043 0.035 0.056 0.057 ? i d(on) on?state drain current v gs = ?4.5 v, v ds = ?5 v ?30 a g fs forward transconductance v ds = ?5 v, i d = ?4.4 a 17 s dynamic characteristics c iss input capacitance 1330 pf c oss output capacitance 552 pf c rss reverse transfer capacitance v ds = ?10 v, v gs = 0 v, f = 1.0 mhz 153 pf switching characteristics (note 2) t d(on) turn?on delay time 12 25 ns t r turn?on rise time 19 40 ns t d(off) turn?off delay time 60 100 ns t f turn?off fall time v dd = ?10 v, i d = ?1 a, v gs = ?4.5 v, r gen = 6 ? 37 70 ns q g total gate charge 14 20 nc q gs gate?source charge 3.0 nc q gd gate?drain charge v ds = ?5 v, i d = ?4.4 a, v gs = ?4.5 v 3.9 nc drain?source diode characteristics and maximum ratings i s maximum continuous drain?source diode forward current ?0.83 a v sd drain?source diode forward voltage v gs = 0 v, i s = ?0.83 a (note 2) ?0.7 ?1.2 v notes: 1. r ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r jc is guaranteed by design while r ca is determined by the user's board design. a) r ja is 125 c/w (steady state) when mounted on a 1 inch2 copper pad on fr-4. b) r ja is 208 c/w (steady state) when mounted on a minimum copper pad on fr-4. 2. pulse test: pulse width < 300 s, duty cycle < 2.0% FDW2502P
FDW2502P rev. d (w) typical characteristics 0 10 20 30 0123 ? v ds , drain-source voltage (v) ? i d , drain current (a) -4.0v -3.0v -2.5v -2.0v v gs = -4.5v -3.5v 0.8 1 1.2 1.4 1.6 1.8 2 0 5 10 15 20 25 30 -i d , drain current (a) r ds(on) , normalized drain-source on-resistance v gs = -2.5v -4.0v -3.5v -4.5v -3.0v figure 1. on-region characteristics. figure 2. on-resistance variation with drain current and gate voltage. 0.6 0.8 1 1.2 1.4 1.6 -50 -25 0 25 50 75 100 125 150 t j , junction temperature ( o c) r ds(on) , normalized drain-source on-resistanc e i d = -4.4a v gs = - 4.5v 0 0.02 0.04 0.06 0.08 0.1 0.12 12345 -v gs , gate to source voltage (v) r ds(on) , on-resistance (ohm) i d = -4.4 a t a = 125 o c t a = 25 o c figure 3. on-resistance variation with temperature. figure 4. on-resistance variation with gate-to-source voltage. 0 5 10 15 20 25 30 01234 -v gs , gate to source voltage (v) -i d , drain current (a) t a = -55 o c 25 o c 125 o v ds = - 5v 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -v sd , body diode forward voltage (v) -i s , reverse drain current (a ) t a = 125 o c 25 o c -55 o c v gs = 0v figure 5. transfer characteristics. figure 6. body diode forward voltage variation with source current and temperature. FDW2502P
FDW2502P rev. d (w) typical characteristics 0 1 2 3 4 5 0 3 6 9 12 15 q g , gate charge (nc) -v gs , gate-source voltage (v) i d = - 4.4a -10v ?15v v ds = - 5v 0 300 600 900 1200 1500 1800 2100 0 5 10 15 20 -v ds , drain to source voltage (v) capacitance (pf) c iss c rss c oss f = 1mhz v gs = 0 v figure 7. gate charge characteristics. figure 8. capacitance characteristics. 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-source voltage (v) dc 10s 1s 100ms r ds(on) limit v gs = 4.5v single pulse r ja = 208 o c/w t a = 25 o c 10ms 1ms 0 10 20 30 40 50 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) single pulse r ja = 208c/w t a = 25c figure 9. maximum safe operating area. figure 10. single pulse maximum power dissipation. 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t 1 , time (sec) r ja (t) = r(t) + r ja r ja =208 c/w t j - t a = p * r ja (t) duty cycle, d = t 1 / t 2 p(pk) t 1 t 2 single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 figure 11. transient thermal response curve. thermal characterization performed using the conditions described in note 1b. transient thermal response will change depending on the circuit board design. FDW2502P
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